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synchronous buck controller with constant on-time and valley current mode adp1870/ADP1871 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features power input voltage range: 2.95 v to 20 v on-board bias regulator minimum output voltage: 0.6 v 0.6 v reference voltage with 1.0% accuracy supports all n-channel mosfet power stages available in 300 khz, 600 khz, and 1.0 mhz options no current-sense resistor required power saving mode (psm) for light loads (ADP1871 only) resistor-programmable current-sense gain thermal overload protection short-circuit protection precision enable input integrated bootstrap diode for high-side drive starts into a precharged load small, 10-lead msop package applications telecom and networking systems mid to high end servers set-top boxes dsp core power supplies general description the adp1870/ADP1871 are versatile current-mode, synchronous step-down controllers that provide superior transient response, optimal stability, and current-limit protection by using a constant on-time, pseudo-fixed frequency with a programmable current- limit, current-control scheme. in addition, these devices offer optimum performance at low duty cycles by utilizing valley current-mode control architecture. this allows the adp1870/ ADP1871 to drive all n-channel power stages to regulate output voltages as low as 0.6 v. the ADP1871 is the power saving mode (psm) version of the device and is capable of pulse skipping to maintain output regulation while achieving improved system efficiency at light loads (see the power saving mode (psm) version (ADP1871) section for more information). available in three frequency options (300 khz, 600 khz, and 1.0 mhz, plus the psm option), the adp1870/ADP1871 are well suited for a wide range of applications that require a single-input power supply range from 2.95 v to 20 v. low voltage biasing is supplied via a 5 v internal ldo. typical applications circuit comp/en bst fb drvh gnd sw vreg drvl pgnd vin c c c vreg c vreg2 c c2 r c r bot r top v out q1 q2 r res l c out v out c bst load c in v in = 2.95v to 20 v adp1870/ ADP1871 08730-001 figure 1. 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 1.8v f sw = 300khz wrth inductor: 744325120, l = 1.2h, dcr = 1.8m ? infineon fets: bsc042n03ms g (upper/lower) v in = 5v (psm) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 08730-102 figure 2. efficiency vs. load current (v out = 1.8 v, 300 khz) in addition, an internally fixed soft start period is included to limit input in-rush current from the input supply during startup and to provide reverse current protection during soft start for a pre- charged output. the low-side current-sense, current-gain scheme and integration of a boost diode, along with the psm/forced pulse- width modulation (pwm) option, reduce the external part count and improve efficiency. the adp1870/ADP1871 operate over the ?40c to +125c junction temperature range and are available in a 10-lead msop package. www..net
adp1870/ADP1871 rev. 0 | page 2 of 44 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? typical applications circuit ............................................................ 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 5 ? thermal resistance ...................................................................... 5 ? boundary condition .................................................................... 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ............................. 6 ? typical performance characteristics ............................................. 7 ? adp1870/ADP1871 block diagram ............................................ 18 ? theory of operation ...................................................................... 19 ? startup .......................................................................................... 19 ? soft start ...................................................................................... 19 ? precision enable circuitry ........................................................ 19 ? undervoltage lockout ............................................................... 19 ? on-board low dropout regulator .......................................... 19 ? thermal shutdown ..................................................................... 20 ? programming resistor (res) detect circuit .......................... 20 ? valley current-limit setting .................................................... 20 ? hiccup mode during short circuit ......................................... 21 ? synchronous rectifier ................................................................ 22 ? power saving mode (psm) version (ADP1871) ................... 22 ? timer operation ........................................................................ 22 ? pseudo-fixed frequency ........................................................... 23 ? applications information .............................................................. 24 ? feedback resistor divider ........................................................ 24 ? inductor selection ...................................................................... 24 ? output ripple voltage (v rr ) .................................................. 24 ? output capacitor selection ....................................................... 24 ? compensation network ............................................................ 25 ? efficiency considerations ......................................................... 26 ? input capacitor selection .......................................................... 27 ? thermal considerations ............................................................ 28 ? design example .......................................................................... 29 ? external component recommendations .................................... 31 ? layout considerations ................................................................... 33 ? ic section (left side of evaluation board) ............................. 37 ? power section ............................................................................. 37 ? differential sensing .................................................................... 38 ? typical applications circuits ........................................................ 39 ? 15 a, 300 khz high current application circuit .................. 39 ? 5.5 v input, 600 khz application circuit ............................... 39 ? 300 khz high current application circuit ............................ 40 ? outline dimensions ....................................................................... 41 ? ordering guide .......................................................................... 41 ? revision history 3/10revision 0: initial version
adp1870/ADP1871 rev. 0 | page 3 of 44 specifications all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). v reg = 5 v, v bst ? v sw = v reg ? v rect_drop (see figure 40 to figure 42 ). v in = 12 v. the specifications are valid for t j = ?40c to +125c, unless otherwise specified. table 1. parameter symbol conditions min typ max unit power supply characteristics high input voltage range v in c in = 22 f to pgnd (at pin 1) adp1870armz-0.3/ADP1871armz-0.3 (300 khz) 2.95 12 20 v adp1870armz-0.6/ADP1871armz-0.6 (600 khz) 2.95 12 20 v adp1870armz-1.0/ADP1871armz-1.0 (1.0 mhz) 3.25 12 20 v quiescent current i q_reg + i q_bst v fb = 1.5 v, no switching 1.1 ma shutdown current i reg,sd + i bst,sd comp/en < 285 mv 190 280 a undervoltage lockout uvlo rising v in (see figure 35 for temperature variation) 2.65 v uvlo hysteresis falling v in from operational state 190 mv internal regulator characteristics vreg operational output voltage v reg c vreg = 1 f to pgnd, 0.22 f to gnd, v in = 2.95 v to 20 v adp1870armz-0.3/ADP1871armz-0.3 (300 khz) 2.75 5 5.5 v adp1870armz-0.6/ADP1871armz-0.6 (600 khz) 2.75 5 5.5 v adp1870armz-1.0/ADP1871armz-1.0 (1.0 mhz) 3.05 5 5.5 v vreg output in regulation v in = 7 v, 100 ma 4.8 4.981 5.16 v v in = 12 v, 100 ma 4.8 4.982 5.16 v load regulation 0 ma to 100 ma, v in = 7 v 32 mv 0 ma to 100 ma, v in = 20 v 33 mv line regulation v in = 7 v to 20 v, 20 ma 2.5 mv v in = 7 v to 20 v, 100 ma 2.0 mv v in to v reg dropout voltage 100 ma out of v reg , v in 5 v 300 415 mv short vreg to pgnd v in = 20 v 229 320 ma soft start soft start period see figure 58 3.0 ms error amplifer fb regulation voltage v fb t j = +25c 600 mv t j = ?40c to +85c 596 600 604 mv t j = ?40c to +125c 594.2 600 605.8 mv transconductance g m 320 496 670 s fb input leakage current i fb, leak v fb = 0.6 v, comp/en = released 1 50 na current-sense amplifier gain programming resistor (res) value from drvl to pgnd res = 47 k 1% 2.7 3 3.3 v/v res = 22 k 1% 5.5 6 6.5 v/v res = none 11 12 13 v/v res = 100 k 1% 22 24 26 v/v switching frequency typical values measured at 50% time points with 0 nf at drvh and drvl; maximum values are guaranteed by bench evaluation 1 adp1870armz-0.3/ ADP1871armz-0.3 (300 khz) 300 khz on-time v in = 5 v, v out = 2 v, t j = 25c 1120 1200 1280 ns minimum on-time v in = 20 v 146 190 ns minimum off-time 84% duty cycle (maximum) 340 400 ns
adp1870/ADP1871 rev. 0 | page 4 of 44 parameter symbol conditions min typ max unit adp1870armz-0.6/ ADP1871armz-0.6 (600 khz) 600 khz on-time v in = 5 v, v out = 2 v, t j = 25c 500 540 580 ns minimum on-time v in = 20 v, v out = 0.8 v 82 110 ns minimum off-time 65% duty cycle (maximum) 340 400 ns adp1870armz-1.0/ ADP1871armz-1.0 (1.0 mhz) 1.0 mhz on-time v in = 5 v, v out = 2 v, t j = 25c 285 312 340 ns minimum on-time v in = 20 v 60 85 ns minimum off-time 45% duty cycle (maximum) 340 400 ns output driver characteristics high-side driver output source resistance i source = 1.5 a, 100 ns, positive pulse (0 v to 5 v) 2.25 3 output sink resistance i sink = 1.5 a, 100 ns, negative pulse (5 v to 0 v) 0.7 1 rise time 2 t r,drvh v bst ? v sw = 4.4 v, c in = 4.3 nf (see figure 60 ) 25 ns fall time 2 t f,drvh v bst ? v sw = 4.4 v, c in = 4.3 nf (see figure 61 ) 11 ns low-side driver output source resistance i source = 1.5 a, 100 ns, positive pulse (0 v to 5 v) 1.6 2.2 output sink resistance i sink = 1.5 a, 100 ns, negative pulse (5 v to 0 v) 0.7 1 rise time 2 t r,drvl v reg = 5.0 v, c in = 4.3 nf (see figure 61 ) 18 ns fall time 2 t f,drvl v reg = 5.0 v, c in = 4.3 nf (see figure 60 ) 16 ns propagation delays drvl fall to drvh rise 2 t tpdhdrvh v bst ? v sw = 4.4 v (see figure 60 ) 15.4 ns drvh fall to drvl rise 2 t tpdhdrvl v bst ? v sw = 4.4 v (see figure 61 ) 18 ns sw leakage current i swleak v bst = 25 v, v sw = 20 v, v reg = 5 v 110 a integrated rectifier channel impedance i sink = 10 ma 22 precision enable threshold logic high level v in = 2.9 v to 20 v, v reg = 2.75 v to 5.5 v 245 285 330 mv enable hysteresis v in = 2.9 v to 20 v, v reg = 2.75 v to 5.5 v 37 mv comp voltage comp clamp low voltage v comp(low) from disabled state, release comp/en pin to enable device (2.75 v v reg 5.5 v) 0.47 v comp clamp high voltage v comp(high) (2.75 v v reg 5.5 v) 2.55 v comp zero current threshold v comp_zct (2.75 v v reg 5.5 v) 1.07 v thermal shutdown t tmsd thermal shutdown threshold rising temperature 155 c thermal shutdown hysteresis 15 c hiccup current limit timing 6 ms 1 the maximum specified values are with the closed loop measured at 10% to 90% time points (see figure and fi gure 61), c gate = 4.3 nf, and the upper- and lower-side mosfets being infi neon bsc042n03msg. 60 2 not automatic test equipment (ate) tested.
adp1870/ADP1871 rev. 0 | page 5 of 44 absolute maximum ratings table 2. parameter rating vreg to pgnd, gnd ?0.3 v to +6 v vin to pgnd ?0.3 v to +28 v fb, comp/en to gnd ?0.3 v to (v reg + 0.3 v) drvl to pgnd ?0.3 v to (v reg + 0.3 v) sw to pgnd ?2.0 v to +28 v bst to sw ?0.6 v to (v reg + 0.3 v) bst to pgnd ?0.3 v to 28 v drvh to sw ?0.3 v to v reg pgnd to gnd 0.3 v ja (10-lead msop) 2-layer board 213.1c/w 4-layer board 171.7c/w operating junction temperature range ?40c to +125c storage temperature range ?65c to +150c soldering conditions jedec j-std-020 maximum soldering lead temperature (10 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unless otherwise specified, all other voltages are referenced to pgnd. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja 1 unit ja (10-lead msop) 2-layer board 213.1 c/w 4- layer board 171.7 c/w 1 ja is specified for the wors t-case conditions; that is, ja is specified for the device soldered in a circuit bo ard for surface-mount packages. boundary condition in determining the values given in table 2 and table 3 , natural convection was used to transfer heat to a 4-layer evaluation board. esd caution
adp1870/ADP1871 rev. 0 | page 6 of 44 pin configuration and fu nction descriptions vin 1 comp/en 2 fb 3 gnd 4 vreg 5 bst 10 sw 9 drvh 8 pgnd 7 drvl 6 adp1870/ ADP1871 top view (not to scale) 08730-003 figure 3. pin configuration table 4. pin function descriptions pin o. mnemonic description 1 vin high input voltage. connect vin to the drain of the upper-side mosfet. 2 comp/en output of the internal error amplifier/ic enable. when this pin functions as en, applying 0 v to this pin disables th e ic. 3 fb noninverting input of the internal error amplifier. this is the node where the feedback resistor is connected. 4 gnd analog ground reference pin of the ic. all sensitive an alog components should be connected to this ground plane (see the layout considerations section). 5 vreg internal regulator supply bias voltage for the adp1870/ ADP1871 controller (includes the output gate drivers). a bypass capacitor of 1 f directly from this pin to pgnd and a 0.1 f across vreg and gnd are recommended. 6 drvl drive output for the external lower-side, n-channel mosf et. this pin also serves as the current-sense gain setting pin (see figure 69 ). 7 pgnd power gnd. ground for the lower-side gate driver and lower-side, n-channel mosfet. 8 drvh drive output for the extern al upper-side, n-channel mosfet. 9 sw switch node connection. 10 bst bootstrap for the upper-side mosfet gate drive circuitry. an internal boot rectifier (diode) is connected between vreg and bst. a capacitor from bst to sw is required. an external schottky diode can also be connected between vreg and bst for increased gate drive capability.
adp1870/ADP1871 rev. 0 | page 7 of 44 typical performance characteristics 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 0.8v f sw = 300khz wrth inductor: 744325072, l = 0.72h, dcr = 1.3m ? infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 08730-104 figure 4. efficiency300 khz, v out = 0.8 v 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 1.8v f sw = 300khz wrth inductor: 744325120, l = 1.2h, dcr = 1.8m ? infineon fets: bsc042n03ms g (upper/lower) v in = 5v (psm) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 08730-105 figure 5. efficiency300 khz, v out = 1.8 v 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 7v f sw = 300khz wrth inductor: 7443551200, l = 2.0h, dcr = 2.6m ? infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 08730-106 figure 6. efficiency300 khz, v out = 7 v 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 0.8v f sw = 600khz wrth inductor: 744355147, l = 0.47h, dcr = 0.67m ? infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 08730-107 figure 7. efficiency600 khz, v out = 0.8 v 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 1.8v f sw = 600khz wrth inductor: 744325072, l = 0.72h, dcr = 1.3m ? infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 08730-108 figure 8. efficiency600 khz, v out = 1.8 v 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 5v f sw = 600khz wrth inductor: 744318180, l = 1.4h, dcr = 3.2m ? infineon fets: bsc042n03ms g (upper/lower) v in = 20v (psm) v in = 13v (psm) v in = 16.5v (psm) v in = 20v v in = 16.5v 08730-109 figure 9. efficiency600 khz, v out = 5 v
adp1870/ADP1871 rev. 0 | page 8 of 44 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 0.8v f sw = 1.0mhz wrth inductor: 744303012, l = 0.12h, dcr = 0.33m ? infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 08730-110 figure 10. efficiency1.0 mhz, v out = 0.8 v 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 1.8v f sw = 1.0mhz wrth inductor: 744303022, l = 0.22h, dcr = 0.33m ? infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 08730-111 figure 11. efficiency1.0 mhz, v out = 1.8 v 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 5v f sw = 1.0mhz wrth inductor: 744355090, l = 0.9h, dcr = 1.6m ? infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 08730-112 figure 12. efficiency1.0 mhz, v out = 5 v 0.807 0.806 0.805 0.804 0.803 0.802 0.801 0.800 0.799 0.798 0.797 0.796 0.795 0.794 0.793 0.792 0 2000 4000 6000 8000 10,000 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 08730-013 figure 13. output voltage accuracy300 khz, v out = 0.8 v 1.821 1.816 1.811 1.806 1.801 1.796 1.791 1.786 0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000 output voltage (v) load current (ma) +125c +25c ?40c v in = 5.5v +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 08730-014 figure 14. output voltage accuracy300 khz, v out = 1.8 v 7.100 7.095 7.090 7.085 7.080 7.075 7.070 7.065 7.060 7.055 7.050 7.045 7.040 7.035 7.030 7.025 7.020 7.015 7.010 7.005 7.000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v v in = 16.5v 08730-015 figure 15. output voltage accuracy300 khz, v out = 7 v
adp1870/ADP1871 rev. 0 | page 9 of 44 0.808 0.792 0.794 0.796 0.798 0.800 0.802 0.804 0.806 0 1000 2000 3000 4000 5000 6000 7000 8000 10,000 9000 frequency (khz) load current (ma) +125c +25c ?40c v in = 13v v in = 16.5v 08730-115 figure 16. output voltage accuracy600 khz, v out = 0.8 v 1.818 1.770 1.772 1.774 1.776 1.778 1.780 1.782 1.784 1.786 1.788 1.790 1.792 1.794 1.796 1.798 1.800 1.802 1.804 1.806 1.808 1.810 1.812 1.814 1.816 0 12,000 10,500 9000 7500 6000 4500 3000 1500 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 08730-016 figure 17. output voltage accuracy600 khz, v out = 1.8 v 5.030 5.025 5.005 5.010 5.015 5.020 5.000 4.995 4.990 4.985 4.980 4.975 4.970 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v v in = 16.5v v in = 20v 08730-017 figure 18. output voltage accuracy600 khz, v out = 5 v 0 2000 4000 6000 8000 10,000 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 08730-118 0.787 0.789 0.791 0.793 0.795 0.797 0.799 0.801 0.803 0.805 0.807 figure 19. output voltage accuracy1.0 mhz, v out = 0.8 v 1.820 1.815 1.810 1.805 1.800 1.795 1.790 0 10,000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 08730-019 figure 20. output voltage accuracy1.0 mhz, v out = 1.8 v 7200 6400 5600 4800 4000 2400 1600 3200 0 9600 8800 8000 800 5.04 4.90 4.91 4.92 4.93 4.94 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 08730-020 figure 21. output voltag e accuracy1.0 mhz, v out =5 v
adp1870/ADP1871 rev. 0 | page 10 of 44 601.0 600.5 600.0 599.5 599.0 598.5 598.0 597.5 597.0 ?40.0 ?7.5 25.0 57.5 90.0 122.5 feedback voltage (v) temperature (c) v reg = 5v, v in = 13v v reg = 5v, v in = 30v 08730-121 figure 22. feedback voltage vs. temperature 325 315 305 295 285 275 265 255 10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 switching frequency (khz) v in (v) +125c +25c ?40c no load 08730-022 figure 23. switching frequency vs. high input voltage, 300 khz, 10% of 12 v 650 600 550 500 450 400 13.0 13.4 13.8 14.2 14.6 15.0 15.4 15.8 16.2 switching frequency (khz) v in (v) +125c +25c ?40c no load 08730-123 figure 24. switching frequency vs. high input voltage, 600 khz, v out = 1.8 v, v in range = 13 v to 16.5 v 900 880 860 840 820 800 780 760 740 720 700 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 switching frequency (khz) v in (v) +125c +25c ?40c 08730-124 figure 25. switching frequency vs. high input voltage, 1.0 mhz, v in range = 13 v to 16.5 v 280 190 205 220 235 250 265 0 10,000 8000 6000 4000 2000 frequency (khz) load current (ma) v in = 13v v in = 20v v in = 16.5v +125c +25c ?40c 08730-025 figure 26. frequency vs. load current, 300 khz, v out = 0.8 v 330 240 250 260 270 280 290 300 310 320 0 15,00 12,000 13,500 10,500 9000 7500 6000 4500 3000 1500 frequency (khz) load current (ma) v in = 20v v in = 13v v in = 16.5v +125c +25c ?40c 08730-026 figure 27. frequency vs. load current, 300 khz, v out = 1.8 v
adp1870/ADP1871 rev. 0 | page 11 of 44 338 298 302 306 310 314 318 322 326 330 334 0 6400 7200 8000 8800 560048004000320024001600 800 frequency (khz) load current (ma) v in = 13v v in = 16.5v +125c +25c ?40c 08730-027 figure 28. frequency vs. load current, 300 khz, v out = 7 v 300 330 360 390 420 450 480 510 540 0 12,000 1200 2400 3600 4800 6000 7200 8400 9600 10,800 frequency (khz) load current (ma) v in = 16.5v v in = 13v +125c +25c ?40c 08730-028 figure 29. frequency vs. load current, 600 khz, v out = 0.8 v 675 495 515 535 555 575 595 615 635 655 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 frequency (khz) load current (ma) v in = 16.5v v in = 13v +125c +25c ?40c 08730-029 figure 30. frequency vs. load current, 600 khz, v out = 1.8 v 740 621 628 635 642 649 656 663 670 677 684 691 698 705 712 719 726 733 0 9600 8800 8000 7200 6400 5600 4800 4000 3200 2400 1600800 frequency (khz) load current (ma) v in = 13v v in = 16.5v +125c +25c ?40c 08730-030 figure 31. frequency vs. load current, 600 khz, v out = 5 v 850 775 700 625 550 475 400 0 12,000 10,000 8000 6000 4000 2000 frequency (khz) load current (ma) v in = 16.5v v in = 13v +125c +25c ?40c 08730-031 figure 32. frequency vs. load current, v out = 1.0 mhz, 0.8 v 550 625 700 775 850 925 1000 1075 1150 1225 0 12,000 9600 10,800 8400 7200 6000 4800 3600 2400 1200 frequency (khz) load current (ma) v in = 16.5v v in = 13v +125c +25c ?40c 08730-032 figure 33. frequency vs. load current, 1.0 mhz, v out = 1.8 v
adp1870/ADP1871 rev. 0 | page 12 of 44 1000 1450 1400 1350 1300 1250 1200 1150 1100 1050 0 8000 800 1600 2400 3200 4000 4800 5600 6400 7200 frequency (khz) load current (ma) v in = 16.5v v in = 13v +125c +25c ?40c 08730-033 figure 34. frequency vs. load current, 1.0 mhz, v out = 5 v 2.649 2.658 2.657 2.656 2.655 2.654 2.653 2.652 2.651 2.650 ?40 120 10080604020 0 ?20 uvlo (v) temperature (c) 08730-034 figure 35. uvlo vs. temperature 55 60 65 70 75 80 85 90 95 300 400 500 600 700 800 900 1000 maximum duty cycle (%) frequency (khz) +125c +25c ?40c 08730-035 figure 36. maximum duty cycle vs. frequency 62 64 66 68 70 72 74 76 78 80 82 5.5 6.7 7.9 9.1 10.3 11.5 12.7 13.9 15.1 16.3 maximum duty cycle (%) v in (v) +125c +25c ?40c 08730-036 figure 37. maximum duty cycle vs. high voltage input (v in ) 180 680 630 580 530 480 430 380 330 280 230 ?40 120 100 80 6040 20 0 ?20 minumum off-time (ns) temperature (c) v reg = 2.7v v reg = 5.5v v reg = 3.6v 08730-037 figure 38. minimum off-time vs. temperature 180 680 630 580 530 480 430 380 330 280 230 2.7 5.5 5.1 4.7 4.3 3.9 3.5 3.1 minumum off-time (ns) v reg (v) +125c +25c ?40c 08730-038 figure 39. minimum off-time vs. v reg (low input voltage)
adp1870/ADP1871 rev. 0 | page 13 of 44 80 800 720 640 560 480 400 320 240 160 300 400 500 600 700 800 900 1000 rectifier drop (mv) frequency (khz) v reg = 2.7v v reg = 5.5v v reg = 3.6v +125c +25c ?40c 08730-039 figure 40. internal rectifier drop vs. frequency 80 1280 720 640 560 480 1040 1120 1200 960 880 800 400 320 240 160 2.73.13.53.94.34.75.15.5 rectifier drop (mv) v reg (v) v in = 5.5v v in = 16.5v v in = 13v 1mhz 300khz t a = 25c 08730-040 figure 41. internal boost rectifier drop vs. v reg (low input voltage) over v in variation 80 720 640 560 480 400 320 240 160 2.73.13.53.94.34.75.15.5 rectifier drop (mv) v reg (v) 1mhz 300khz +125c +25c ?40c 08730-041 figure 42. internal boost rectifier drop vs. v reg 8 80 64 72 56 48 40 32 24 16 2.73.13.53.94.34.75.15.5 body diode conduction time (ns) v reg (v) 1mhz 300khz +125c +25c ?40c 08730-042 figure 43. lower-side mosfet body diode conduction time vs. v reg ch1 50mv b w ch2 5a ? ch3 10v b w ch4 5v m400ns a ch2 3.90a t 35.8% 1 2 3 4 output voltage inductor current sw node low side 08730-043 figure 44. power saving mode (psm) operational waveform, 100 ma ch1 50mv b w ch2 5a ? ch3 10v b w ch4 5v m4.0s a ch2 3.90a t 35.8% 1 2 3 4 output voltage inductor current sw node low side 08730-044 figure 45. psm waveform at light load, 500 ma
adp1870/ADP1871 rev. 0 | page 14 of 44 ch1 5a ? ch3 10v ch4 100mv b w m400ns a ch3 2.20v t 30.6% 1 3 4 output voltage inductor current sw node 08730-045 figure 46. ccm operation at heavy load, 12 a (see figure 93 for application circuit) ch1 10a ? ch2 200mv b w ch3 20v ch4 5v m2ms a ch1 3.40a t 75.6% 1 2 3 4 output voltage 12a step sw node low side 08730-046 figure 47. load transient steppsm enabled, 12 a (see figure 93 application circuit) ch1 10a ? ch2 200mv b w ch3 20v ch4 5v m20s a ch1 3.40a t 30.6% 1 2 3 4 output voltage 12a positive step sw node low side 08730-047 figure 48. positive step during heavy load transient behaviorpsm enabled, 12 a, v out = 1.8 v (see figure 93 application circuit) ch1 10a ? ch2 200mv b w ch3 20v ch4 5v m20s a ch1 3.40a t 48.2% 1 2 3 4 output voltage 12a negative step sw node low side 08730-048 figure 49. negative step during heavy load transient behaviorpsm enabled, 12 a (see figure 93 application circuit) ch1 10a ? ch2 5v ch3 20v ch4 200mv b w m2ms a ch1 6.20a t 15.6% 1 2 3 4 output voltage 12a step sw node low side 08730-049 figure 50. load transient stepforced pwm at light load, 12 a (see figure 93 application circuit) ch1 10a ? ch2 5v ch3 20v ch4 200mv b w m20s a ch1 6.20a t 43.8% 1 2 3 4 output voltage 12a positive step sw node low side 08730-050 figure 51. positive step during heavy load transient behaviorforced pwm at light load, 12 a, v out = 1.8 v (see figure 93 application circuit)
adp1870/ADP1871 rev. 0 | page 15 of 44 ch1 10a ? ch2 200mv b w ch3 20v ch4 5v m10s a ch1 5.60a t 23.8% 1 2 3 4 output voltage 12a negative step sw node low side 08730-051 figure 52. negative step during heavy load transient behaviorforced pwm at light load, 12 a (see figure 93 application circuit) ch1 2v b w ch2 5a ? ch3 10v ch4 5v m4ms a ch1 920mv t 49.4% 1 2 3 4 output voltage inductor current sw node low side 08730-052 figure 53. output short-circuit behavior leading to hiccup mode ch1 5v b w ch2 10a ? ch3 10v ch4 5v m10s a ch2 8.20a t 36.2% 1 2 3 4 output voltage inductor current sw node low side 08730-053 figure 54. magnified waveform during hiccup mode ch1 2v b w ch2 5a ? ch3 10v ch4 5v m2ms a ch1 720mv t 32.8% 1 2 3 4 output voltage inductor current sw node low side 08730-054 figure 55. start-up behavior at heavy load, 12 a, 300 khz (see figure 93 application circuit) ch1 2v b w ch2 5a ? ch3 10v ch4 5v m4ms a ch1 720mv t 41.6% 1 2 3 4 output voltage inductor current sw node low side 08730-055 figure 56. power-down waveform during heavy load ch1 50mv b w ch2 5a ? ch3 10v b w ch4 5v m2s a ch2 3.90a t 35.8% 1 2 3 4 output voltage inductor current sw node low side 08730-056 figure 57. output voltage ripple waveform during psm operation at light load, 2 a
adp1870/ADP1871 rev. 0 | page 16 of 44 ch1 1v b w ch2 5a ? ch3 10v b w ch4 2v m1ms a ch1 1.56v t 63.2% 1 2 3 4 output voltage inductor current sw node low side 08730-057 figure 58. soft start and res detect waveform 2 ch2 5v ch3 5v math 2v 40ns ch4 2v m40ns a ch2 4.20v t 29.0% 3 m 4 high side hs minus sw sw node low side t a = 25c 08730-058 figure 59. output driver s and sw node waveforms 2 ch2 5v ch3 5v math 2v 40ns ch4 2v m40ns a ch2 4.20v t 29.0% 3 m 4 high side hs minus sw sw node low side 16ns ( t f ,drvl ) 25ns ( t r ,drvh ) 22ns ( t pdh drvh ) t a = 25c 08730-059 figure 60. upper-side driver rising and lower-side falling edge waveforms (c in = 4.3 nf (upper-/lower-side mosfet), q total = 27 nc (v gs = 4.4 v (q1), v gs = 5 v (q3)) 2 ch2 5v ch3 5v math 2v 20ns ch4 2v m20ns a ch2 4.20v t 39.2% 3 m 4 high side hs minus sw sw node low side 18ns ( t r ,drvl ) 24ns ( t pdh ,drvl ) 11ns ( t f ,drvh ) t a = 25c 08730-060 figure 61. upper-side driver falling an d lower-side rising edge waveforms (c in = 4.3 nf (upper-/lower-side mosfet), q total = 27 nc (v gs = 4.4 v (q1), v gs = 5 v (q3)) 570 550 530 510 490 470 450 430 ?40 ?20 120 10080604020 0 transconductance (s) temperature (c) v reg = 5.5v v reg = 3.6v v reg = 2.7v 08730-061 figure 62. transconductance (g m ) vs. temperature 680 330 380 430 480 530 580 630 2.7 3.0 5.4 4.8 5.1 4.5 4.2 3.93.6 3.3 transconductance (s) v reg (v) +125c +25c ?40c 08730-062 figure 63. transconductance (g m ) vs. v reg
adp1870/ADP1871 rev. 0 | page 17 of 44 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 0.75 0.70 2.7 5.5 5.1 4.7 4.3 ?40c +25c +125c 3.9 3.5 3.1 quiescent current (ma) v reg (v) 08730-163 figure 64. quiescent current vs. v reg
adp1870/ADP1871 rev. 0 | page 18 of 44 adp1870/ADP1871 block diagram drvh gnd i rev comp adp1870/ADP1871 c r (trimmed) vreg t on timer t on = 2rc(v out /v in ) i sw information sw filter state machine ton bg_ref bg_ref bg_ref inl_hicc bg_ref hi sw lo bg_ref level shift hs vreg ls vreg 300k? 8k? sw drvl pgnd bst vin psm ref_zero ss comp error amp ss_ref 0.6v lower comp clamp ref_zero cs amp pwm fb comp/ en vreg i ss c ss 0.4v adc res detect and gain set cs gain set bias block and reference ref ldo precision enable block to enable all blocks 08730-063 figure 65. adp1870/ADP1871 block diagram
adp1870/ADP1871 rev. 0 | page 19 of 44 theory of operation the adp1870/ADP1871 are versatile current-mode, synchronous step-down controllers that provide superior transient response, optimal stability, and current limit protection by using a constant on-time, pseudo-fixed frequency with a programmable current- sense gain, current-control scheme. in addition, these devices offer optimum performance at low duty cycles by utilizing valley current-mode control architecture. this allows the adp1870/ ADP1871 to drive all n-channel power stages to regulate output voltages as low as 0.6 v. startup the adp1870/ADP1871 have an internal regulator (vreg) for biasing and supplying power for the integrated mosfet drivers. a bypass capacitor should be located directly across the vreg (pin 5) and pgnd (pin 7) pins. included in the power-up sequence is the biasing of the current-sense amplifier, the current-sense gain circuit (see the programming resistor (res) detect circuit section), the soft start circuit, and the error amplifier. the current-sense blocks provide valley current information (see the programming resistor (res) detect circuit section) and are a variable of the compensation equation for loop stability (see the compensation network section). the valley current information is extracted by forcing 0.4 v across the drvl output and pgnd pin, which generates a current depending on the resistor across drvl and pgnd in a process performed by the res detect circuit. the current through the resistor is used to set the current-sense amplifier gain. this process takes approximately 800 s, after which the drive signal pulses appear at the drvl and drvh pins synchronously and the output voltage begins to rise in a controlled manner through the soft start sequence. the rise time of the output voltage is determined by the soft start and error amplifier blocks (see the soft start section). at the beginning of a soft start, the error amplifier charges the external compensation capacitor, causing the comp/en pin to rise above the enable threshold of 285 mv, thus enabling the adp1870/ADP1871. soft start the adp1870/ADP1871 have digital soft start circuitry, which involves a counter that initiates an incremental increase in current, by 1 a, via a current source on every cycle through a fixed internal capacitor. the output tracks the ramping voltage by producing pwm output pulses to the upper-side mosfet. the purpose is to limit the in-rush current from the high voltage input supply (v in ) to the output (v out ). precision enable circuitry the adp1870/ADP1871 employ precision enable circuitry. the enable threshold is 285 mv typical with 35 mv of hysteresis. the devices are enabled when the comp/en pin is released, allowing the error amplifier output to rise above the enable threshold (see figure 66 ). grounding this pin disables the adp1870/ADP1871, reducing the supply current of the devices to approximately 140 a. for more information, see figure 67 . 0.6v 285mv ss vreg fb comp/en precision enable error amplifier to enable all blocks c c c c2 r c adp1870/ADP1871 08730-064 figure 66. release comp/en pin to enable the adp1870/ADP1871 comp/en >2.4v 2.4v 1.0v 500mv 285mv 0v hiccup mode initialized maximum current (upper clamp) zero current usable range only after soft start period if contunuous conduction mode of operation is selected. lower clamp precision enable threshold 35mv hysteresis 08730-065 figure 67. comp/en voltage range undervoltage lockout the undervoltage lockout (uvlo) feature prevents the part from operating both the upper- and lower-side mosfets at extremely low or undefined input voltage (v in ) ranges. operation at an undefined bias voltage may result in the incorrect propagation of signals to the high-side power switches. this, in turn, results in invalid output behavior that can cause damage to the output devices, ultimately destroying the device tied at the output. the uvlo level has been set at 2.65 v (nominal). on-board low dropout regulator the adp1870 uses an on-board ldo to bias the internal digital and analog circuitry. with proper bypass capacitors connected to the vreg pin (output of internal ldo), this pin also provides power for the internal mosfet drivers. it is recommended to float vreg if vin is utilized for greater than 5.5 v operation. the minimum voltage where bias is guaranteed to operate is 2.75 v at vreg. for applications where vin is decoupled from vreg, the minimum voltage at vin must be 2.9 v. it is recommended that
adp1870/ADP1871 rev. 0 | page 20 of 44 vin and vreg be tied together if the vin pin is subjected to a 2.75 v rail. table 5. power input and ldo output configurations vin vreg comments >5.5 v float must use the ldo <5.5 v connect to vin ldo drop voltage is not realized (that is, if v in = 2.75 v, then v reg = 2.75 v) <5.5 v float ldo drop is realized ranges above and below 5.5 v float ldo drop is realized, minimum v in recom- mendation is 2.95 v thermal shutdown the thermal shutdown is a self-protection feature to prevent the ic from damage due to a very high operating junction temperature. if the junction temperature of the device exceeds 155c, the part enters the thermal shutdown state. in this state, the device shuts off both the upper- and lower-side mosfets and disables the entire controller immediately, thus reducing the power consumption of the ic. the part resumes operation after the junction temperature of the part cools to less than 140c. programming resistor (res) detect circuit upon startup, one of the first blocks to become active is the res detect circuit. this block powers up before soft start begins. it forces a 0.4 v reference value at the drvl output (see figure 68 ) and is programmed to identify four possible resistor values: 47 k, 22 k, open, and 100 k. the res detect circuit digitizes the value of the resistor at the drvl pin (pin 6). an internal adc outputs a 2-bit digital code that is used to program four separate gain configurations in the current-sense amplifier (see figure 69 ). each configuration corre- sponds to a current-sense gain (a cs ) of 3 v/v, 6 v/v, 12 v/v, 24 v/v, respectively (see table 6 and table 7 ). this variable is used for the valley current-limit setting, which sets up the appropriate current-sense gain for a given application and sets the compensation necessary to achieve loop stability (see the valley current-limit setting and compensation network sections). drvh drvl q1 sw q2 r res adp1870/ ADP1871 cs gain programming 08730-066 figure 68. programming resistor location sw pgnd cs gain set cs amp adc drvl res 0.4v 08730-067 figure 69. res detect circuit for current-sense gain programming table 6. current-sense gain programming resistor a cs 47 k 3 v/v 22 k 6 v/v open 12 v/v 100 k 24 v/v valley current-limit setting the architecture of the adp1870/ADP1871 is based on valley current-mode control. the current limit is determined by three components: the r on of the lower-side mosfet, the error ampli- fier output voltage swing (comp), and the current-sense gain. the comp range is internally fixed at 1.4 v. the current-sense gain is programmable via an external resistor at the drvl pin (see the programming resistor (res) detect circuit section). the r on of the lower-side mosfet can vary over temperature and usually has a positive t c (meaning that it increases with tempera- ture); therefore, it is recommended to program the current-sense gain resistor based on the rated r on of the mosfet at 125c. because the adp1870/ADP1871 are based on valley current control, the relationship between i clim and i load is as follows: ? ? ? ? ? ? ?= 2 1 i load clim k ii where: k i is the ratio between the inductor ripple current and the desired average load current (see figure 70 ). i clim is the desired valley current limit. i load is the current load. establishing k i helps to determine the inductor value (see the inductor selection section), but in most cases k i = 0.33. load current valley current limit ripple current = i load 3 0 8730-068 figure 70. valley current limit to average current relation
adp1870/ADP1871 rev. 0 | page 21 of 44 when the desired valley current limit (i clim ) has been determined, the current-sense gain can be calculated as follows: the valley current limit is programmed as outlined in table 7 and figure 71 . the inductor chosen must be rated to handle the peak current, which is equal to the valley current from table 7 plus the peak-to-peak inductor ripple current (see the inductor selection section). in addition, the peak current value must be used to compute the worst-case power dissipation in the mosfets (see figure 72 ). oncs clim ra i = v4.1 where: r on is the channel impedance of the lower-side mosfet. a cs is the current-sense gain multiplier (see table 6 and table 7 ). inductor current valley current-limit threshold (set for 25a) ? i = 33% of 30a comp output swing comp output 2.4v 1v 0a 35a 30a 32.25a 37a 49 a 39.5a ? i = 45% of 32.25a ? i = 65% of 37a maximum dc load current 08730-070 although the adp1870/ADP1871 have only four discrete current- sense gain settings for a given r on variable, table 7 and figure 71 outline several available options for the valley current setpoint based on various r on values. table 7. valley current limit program 1 r o m valley current level 47 22 open 100 cs 3 v/v cs 6 v/v cs 12 v/v cs 24 v/v 1.5 38.9 2 29.2 2.5 23.3 3 39.0 19.5 3.5 33.4 16.7 4.5 26.0 13 5 23.4 11.7 5.5 21.25 10.6 10 23.3 11.7 5.83 15 31.0 15.5 7.75 7.5 18 26.0 13.0 6.5 3.25 figure 72. valley current-limit threshold in relation to inductor ripple current hiccup mode during short circuit a current-limit violation occurs when the current across the source and drain of the lower-side mosfet exceeds the current-limit setpoint. when 32 current-limit violations are detected, the controller enters idle mode and turns off the mosfets for 6 ms, allowing the converter to cool down. then, the controller reestablishes soft start and begins to cause the output to ramp up again (see figure 73 ). while the output ramps up, comp is monitored to determine if the violation is still present. if it is still present, the idle event occurs again, followed by the full-chip power-down sequence. this cycle continues until the violation no longer exists. if the violation disappears, the converter is allowed to switch normally, maintaining regulation. 1 refer to figure 71 for more information and a graphical representation. 1234567891011121314151617181920 valley current limit (a) r on (m ? ) 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 res = 47k ? a cs = 3v/v res = 22k ? a cs = 6v/v res = no res a cs = 12v/v res = 100k ? a cs = 24v/v 08730-069 figure 71. valley current-limit value vs. r on of the lower-side mosfet for each programming resistor (res) hs clim zero current repeated current-limit violation detected a predetermined number of pulses is counted to allow the converter to cool down soft start is reinitialized to monitor if the violation still exists 08730-071 figure 73. idle mode entry sequence due to current-limit violation
adp1870/ADP1871 rev. 0 | page 22 of 44 synchronous rectifier the adp1870/ADP1871 employ an internal lower-side mosfet driver to drive the external upper- and lower-side mosfets. the synchronous rectifier not only improves overall conduction efficiency, but also ensures proper charging to the bootstrap capacitor located at the upper-side driver input. this is beneficial during startup to provide sufficient drive signal to the external upper-side mosfet and to attain fast turn-on response, which is essential for minimizing switching losses. the integrated upper- and lower-side mosfet drivers operate in complementary fashion with built-in anticross conduction circuitry to prevent unwanted shoot-through current that may potentially damage the mosfets or reduce efficiency as a result of excessive power loss. power saving mode (psm) version (ADP1871) the power saving mode version of the adp1870 is the ADP1871. the ADP1871 operates in the discontinuous conduction mode (dcm) and pulse skips at light load to mid load currents. it outputs pulses as necessary to maintain output regulation. unlike the continuous conduction mode (ccm), dcm operation prevents negative current, thus allowing improved system efficiency at light loads. current in the reverse direction through this pathway, however, results in power dissipation and therefore a decrease in efficiency. hs hs and ls are off or in idle mode ls 0a i load as the inductor current approaches zero current, the state machine turns off the lower-side mosfet. t on t off 08730-072 figure 74. discontinuous mode of operation (dcm) to minimize the chance of negative inductor current buildup, an on-board zero-cross comparator turns off all upper- and lower-side switching activities when the inductor current approaches the zero current line, causing the system to enter idle mode, where the upper- and lower-side mosfets are turned off. to ensure idle mode entry, a 10 mv offset, connected in series at the sw node, is implemented (see figure 75 ). 10mv zero-cross comparator q2 ls sw i q2 08730-073 figure 75. zero-cross comparator with 10 mv of offset as soon as the forward current through the lower-side mosfet decreases to a level where 10 mv = i q2 r on(q2) the zero-cross comparator (or i rev comparator) emits a signal to turn off the lower-side mosfet. from this point, the slope of the inductor current ramping down becomes steeper (see figure 76 ) as the body diode of the lower-side mosfet begins to conduct current and continues conducting current until the remaining energy stored in the inductor has been depleted. hs and ls in idle mode 10mv = r on i load zero-cross comparator detects 10mv offset and turns off ls sw ls 0a i load t on another t on edge is triggered when v out falls below regulation 08730-074 figure 76. 10 mv offset to ensure pr evention of negative inductor current the system remains in idle mode until the output voltage drops below regulation. a pwm pulse is then produced, turning on the upper-side mosfet to maintain system regulation. the ADP1871 does not have an internal clock, so it switches purely as a hysteretic controller as described in this section. timer operation the adp1870/ADP1871 employ a constant on-time architecture, which provides a variety of benefits, including improved load and line transient response when compared with a constant (fixed) frequency current-mode control loop of comparable loop design. the constant on-time timer, or t on timer, senses the high input voltage (v in ) and the output voltage (v out ) using sw waveform information to produce an adjustable one-shot pwm pulse that varies the on-time of the upper-side mosfet in response to dynamic changes in input voltage, output voltage, and load current conditions to maintain regulation. it then generates an on-time (t on ) pulse that is inversely proportional to v in. in out on v v kt = where: k is a constant that is trimmed using an rc timer product for the 300 khz, 600 khz, and 1.0 mhz frequency options.
adp1870/ADP1871 rev. 0 | page 23 of 44 c r (t rimmed) vreg t on v in i to illustrate this feature more clearly, this section describes one such load transient eventa positive load stepin detail. during load transient events, the high-side driver output pulse width stays relatively consistent from cycle to cycle; however, the off-time (drvl on-time) dynamically adjusts according to the instantaneous changes in the external conditions mentioned. sw information when a positive load step occurs, the error amplifier (out of phase of the output, v out ) produces new voltage information at its output (comp). in addition, the current-sense amplifier senses new inductor current information during this positive load transient event. the error amplifiers output voltage reaction is compared with the new inductor current information that sets the start of the next switching cycle. because current information is produced from valley current sensing, it is sensed at the down ramp of the inductor current, whereas the voltage loop information is sensed through the counter action upswing of the error amplifiers output (comp). 08730-075 figure 77. constant on-time time the constant on-time (t on ) is not strictly constant because it varies with v in and v out . however, this variation occurs in such a way as to keep the switching frequency virtually independent of v in and v out . the t on timer uses a feedforward technique, applied to the constant on-time control loop, making it a pseudo-fixed frequency to a first order. second-order effects, such as dc losses in the external power mosfets (see the efficiency consideration section), cause some variation in frequency vs. load current and line voltage. these effects are shown in figure 23 to figure 34 . the variations in frequency are much reduced compared with the variations generated when the feedforward technique is not utilized. the result is a convergence of these two signals (see figure 78 ), which allows an instantaneous increase in switching frequency during the positive load transient event. in summary, a positive load step causes v out to transient down, which causes comp to transient up and therefore shortens the off-time. this resulting increase in frequency during a positive load transient helps to quickly bring v out back up in value and within the regulation window. the feedforward technique establishes the following relationship: k f sw 1 = where f sw is the controller switching frequency (300 khz, 600 khz, and 1.0 mhz). similarly, a negative load step causes the off-time to lengthen in response to v out rising. this effectively increases the inductor demagnetizing phase, helping to bring v out within regulation. in this case, the switching frequency decreases, or experiences a foldback, to help facilitate output voltage recovery. the t on timer senses v in and v out to minimize frequency variation as previously explained. this provides a pseudo-fixed frequency as explained in the pseudo-fixed frequency section. to allow headroom for v in and v out sensing, adhere to the following equations: because the adp1870/ADP1871 has the ability to respond rapidly to sudden changes in load demand, the recovery period in which the output voltage settles back to its original steady state operating point is much quicker than it would be for a fixed-frequency equivalent . therefore, using a pseudo-fixed frequency results in significantly better load transient performance than using a fixed frequency. v reg v in /8 + 1.5 v reg v out /4 for typical applications where v reg is 5 v, these equations are not relevant; however, for lower v reg inputs, care may be required. valley trip points load current demand error amp output pwm output f sw > f sw cs amp output 08730-076 pseudo-fied frequency the adp1870/ADP1871 employ a constant on-time control scheme. during steady state operation, the switching frequency stays relatively constant, or pseudo-fixed. this is due to the one- shot t on timer that produces a high-side pwm pulse with a fixed duration, given that external conditions such as input voltage, output voltage, and load current are also at steady state. during load transients, the frequency momentarily changes for the duration of the transient event so that the output comes back within regulation more quickly than if the frequency were fixed or if it were to remain unchanged. after the transient event is complete, the frequency returns to a pseudo-fixed frequency value to a first order. figure 78. load transient response operation
adp1870/ADP1871 rev. 0 | page 24 of 44 applications information feedback resistor divider the required resistor divider network can be determined for a given v out value because the internal band gap reference (v ref ) is fixed at 0.6 v. selecting values for r t and r b determines the minimum output load current of the converter. therefore, for a given value of r b , the r t value can be determined through the following expression: v6.0 v)6.0( ? = out b t v rr inductor selection the inductor value is inversely proportional to the inductor ripple current. the peak-to-peak ripple current is given by 3 load load il i iki ?= where k i is typically 0.33. the equation for the inductor value is given by in out sw l out in v v fi vv l ? = ) ( where: v in is the high voltage input. v out is the desired output voltage. f sw is the controller switching frequency (300 khz, 600 khz, and 1.0 mhz). when selecting the inductor, choose an inductor saturation rating that is above the peak current level, and then calculate the inductor current ripple (see the valley current-limit setting section and figure 79 ). 52 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 6 8 10 12 14 16 18 20 22 24 26 28 30 peak inductor current (a) valley current limit (a) ? i = 50% ? i = 40% ? i = 33% 08730-077 figure 79. peak inductor current vs. valley current limit for 33%, 40%, and 50% of inductor ripple current table 8. recommended inductors l (h) dcr (m) i sat (a) dimensions (mm) manufacturer model number 0.12 0.33 55 10.2 7 wrth elek. 744303012 0.22 0.33 30 10.2 7 wrth elek. 744303022 0.47 0.67 50 13.2 12.8 wrth elek. 744355147 0.72 1.3 35 10.5 10.2 wrth elek. 744325072 0.9 1.6 28 13 12.8 wrth elek. 744355090 1.2 1.8 25 10.5 10.2 wrth elek. 744325120 1.0 3.3 20 10.5 10.2 wrth elek. 7443552100 1.4 3.2 24 14 12.8 wrth elek. 744318180 2.0 2.6 22 13.2 12.8 wrth elek. 7443551200 0.8 2.5 16.5 12.5 12.5 aic technology cep125u-r80 output ripple voltage (v rr ) the output ripple voltage is the ac component of the dc output voltage during steady state. for a ripple error of 1.0%, the output capacitor value needed to achieve this tolerance can be determined using the following equation. (note that an accuracy of 1.0% is possible only during steady state conditions, not during load transients.) out rr v v = )01.0( output capacitor selection the primary objective of the output capacitor is to facilitate the reduction of the output voltage ripple; however, the output capacitor also assists in the output voltage recovery during load transient events. for a given load current step, the output voltage ripple generated during this step event is inversely proportional to the value chosen for the output capacitor. the speed at which the output voltage settles during this recovery period depends on where the crossover frequency (loop bandwidth) is set. this crossover frequency is determined by the output capacitor, the equivalent series resistance (esr) of the capacitor, and the compensation network. to calculate the small-signal voltage ripple (output ripple voltage) at the steady state operating point, use the following equation: [] ? ? ? ? ? ? ? ? ?? = )( 8 1 esrivf ic l ripple sw l out where esr is the equivalent series resistance of the output capacitors. to calculate the output load step, use the following equation: )) ( ( 2 esri vf i c load droop sw load out ?? = where v droop is the amount that v out is allowed to deviate for a given positive load current step (i load ).
adp1870/ADP1871 rev. 0 | page 25 of 44 ceramic capacitors are known to have low esr. however, the trade-off of using x5r technology is that up to 80% of its capaci- tance might be lost due to derating as the voltage applied across the capacitor is increased (see figure 80 ). although x7r series capacitors can also be used, the available selection is limited to only up to 22 f. 20 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 5 10 15 20 25 30 capacitance charge (%) dc voltage (v dc ) x7r (50v) x5r (25v) x5r (16v) 10f tdk 25v, x7r, 1210 c3225x7r1e106m 22f murata 25v, x7r, 1210 grm32er71e226ke15l 47f murata 16v, x5r, 1210 grm32er61c476ke15l 08730-078 figure 80. capacitance vs. dc voltage characteristics for ceramic capacitors electrolytic capacitors satisfy the bulk capacitance requirements for most high current applications. because the esr of electrolytic capacitors is much higher than that of ceramic capacitors, when using electrolytic capacitors, several mlccs should be mounted in parallel to reduce the overall series resistance. compensation network due to their current-mode architecture, the adp1870/ADP1871 require type ii compensation. to determine the component values needed for compensation (resistance and capacitance values), it is necessary to examine the converters overall loop gain (h) at the unity gain frequency (f sw /10) when h = 1 v/v: filt comp ref out cs m zz v v gg h == v/v 1 examining each variable at high frequency enables the unity- gain transfer function to be simplified to provide expressions for the r comp and c comp component values. output filter impedance (z filt ) examining the filters transfer function at high frequencies simplifies to out filter sc z 1 = at the crossover frequency (s = 2f cross ). error amplifier output impedance (z comp ) assuming that c c2 is significantly smaller than c comp , c c2 can be omitted from the output impedance equation of the error amplifier. the transfer function simplifies to cross zero cross comp comp f ffr z ) ( + = and sw cross f f = 12 1 where f zero , the zero frequency, is set to be 1/4 th of the crossover frequency for the adp1870. error amplifier gain (g m ) the error amplifier gain (transconductance) is g m = 500 a/v current-sense loop gain (g cs ) the current-sense loop gain is oncs cs ra g = 1 (a/v) where: a cs (v/v) is programmable for 3 v/v, 6 v/v, 12 v/v, and 24 v/v (see the programming resistor (res) detect circuit and va l le y current-limit setting sections). r on is the channel impedance of the lower-side mosfet. crossover frequency the crossover frequency is the frequency at which the overall loop (system) gain is 0 db (h = 1 v/v). for current-mode converters, such as the adp1870, it is recommended that the user set the crossover frequency between 1/10 th and 1/15 th of the switching frequency. sw cross ff 12 1 = the relationship between c comp and f zero (zero frequency) is as follows: comp comp zero cr f = 2 1 ) the zero frequency is set to 1/4 th of the crossover frequency. combining all of the above parameters results in ref out cs m out cross zero cross cross comp v v gg cf ff f r + = 2 zero comp comp fr c = 2 1
adp1870/ADP1871 rev. 0 | page 26 of 44 efficiency considerations one of the important criteria to consider in constructing a dc-to-dc converter is efficiency. by definition, efficiency is the ratio of the output power to the input power. for high power applications at load currents up to 20 a, the following are important mosfet parameters that aid in the selection process: ? v gs (th) : the mosfet support voltage applied between the gate and the source ? r ds (on) : the mosfet on resistance during channel conduction ? q g : the total gate charge ? c n1 : the input capacitance of the upper-side switch ? c n2 : the input capacitance of the lower-side switch the following are the losses experienced through the external component during normal switching operation: ? channel conduction loss (both of the mosfets) ? mosfet driver loss ? mosfet switching loss ? body diode conduction loss (lower-side mosfet) ? inductor loss (copper and core loss) channel conduction loss during normal operation, the bulk of the loss in efficiency is due to the power dissipated through mosfet channel conduction. power loss through the upper-side mosfet is directly pro- portional to the duty cycle (d) for each switching period, and the power loss through the lower-side mosfet is directly proportional to 1 ? d for each switching period. the selection of mosfets is governed by the amount of maximum dc load current that the converter is expected to deliver. in particular, the selection of the lower-side mosfet is dictated by the maximum load current because a typical high current application employs duty cycles of less than 50%. therefore, the lower-side mosfet is in the on state for most of the switching period. () [ ] 2 1 load n2(on) n1(on) n1,n2(cl) ird rd p ?+= mosfet driver loss other dissipative elements are the mosfet drivers. the con- tributing factors are the dc current flowing through the driver during operation and the q gate parameter of the external mosfets. ( ) [ ] () [] bias reg lowerfet sw reg bias dr upperfet sw dr lossdr ivcfv ivcfv p + ++ = )( where: c upperfet is the input gate capacitance of the upper-side mosfet. c lowerfet is the input gate capacitance of the lower-side mosfet. i bias is the dc current flowing into the upper- and lower-side drivers. v dr is the driver bias voltage (that is, the low input voltage (v reg ) minus the rectifier drop (see figure 81 )). v reg is the bias voltage. f sw is the controller switching frequency (300 khz, 600 khz, and 1.0 mhz) 800 720 640 560 480 400 320 240 160 80 300 1000 900 800 700 600 500 400 rectifier drop (mv) switching frequency (khz) +125c +25c 40c v reg = 2.7v v reg = 3.6v v reg = 5.5v 08730-079 figure 81. internal rectifier voltage drop vs. switching frequency switching loss the sw node transitions due to the switching activities of the upper- and lower-side mosfets. this causes removal and replenishing of charge to and from the gate oxide layer of the mosfet, as well as to and from the parasitic capacitance associated with the gate oxide edge overlap and the drain and source terminals. the current that enters and exits these charge paths presents additional loss during these transition times. this loss can be approximately quantified by using the following equation, which represents the time in which charge enters and exits these capacitive regions: t sw-trans = r gate c total where: c total is the c gd + c gs of the external mosfet. r gate is the gate input resistance of the external mosfet. the ratio of this time constant to the period of one switching cycle is the multiplying factor to be used in the following expression: 2 - )( = or 2 )( =
adp1870/ADP1871 rev. 0 | page 27 of 44 diode conduction loss the adp1870/ADP1871 employ anticross conduction circuitry that prevents the upper- and lower-side mosfets from conducting current simultaneously. this overlap control is beneficial, avoiding large current flow that may lead to irreparable damage to the external components of the power stage. however, this blanking period comes with the trade-off of a diode conduction loss occurring immediately after the mosfets change states and continuing well into idle mode. the amount of loss through the body diode of the lower-side mosfet during the antioverlap state is given by the following expression: 2 )( )( = f load sw loss body loss body vi t t p where: t body(loss) is the body conduction time (refer to figure 82 for dead time periods). t sw is the period per switching cycle. v f is the forward drop of the body diode during conduction. (refer to the selected external mosfet data sheet for more information about the v f parameter.) 80 72 64 56 48 40 32 24 16 8 2.7 5.5 4.8 4.1 3.4 body diode conduction time (ns) v reg (v) +125c +25c ?40c 1mhz 300khz 08730-080 figure 82. body diode conduction time vs. low voltage input (v reg ) inductor loss during normal conduction mode, further power loss is caused by the conduction of current through the inductor windings, which have dc resistance (dcr). typically, larger sized inductors have smaller dcr values. the inductor core loss is a result of the eddy currents generated within the core material. these eddy currents are induced by the changing flux, which is produced by the current flowing through the windings. the amount of inductor core loss depends on the core material, the flux swing, the frequency, and the core volume. ferrite inductors have the lowest core losses, whereas powdered iron inductors have higher core losses. it is recommended that shielded ferrite core material type inductors be used with the adp1870/ADP1871 for a high current, dc-to-dc switching application to achieve minimal loss and negligible electromagnetic interference (emi). 2 )( load lossdcr idcr p = + core loss input capacitor selection the goal in selecting an input capacitor is to reduce or minimize input voltage ripple and to reduce the high frequency source impedance, which is essential for achieving predictable loop stability and transient performance. the problem with using bulk capacitors, other than their physical geometries, is their large equivalent series resistance (esr) and large equivalent series inductance (esl). aluminum electrolytic capacitors have such high esr that they cause undesired input voltage ripple magnitudes and are generally not effective at high switching frequencies. if bulk capacitors are to be used, it is recommended that muli- layered ceramic capacitors (mlcc) be used in parallel due to their low esr values. this dramatically reduces the input voltage ripple amplitude as long as the mlccs are mounted directly across the drain of the upper-side mosfet and the source terminal of the lower-side mosfet (see the layout considerations section). improper placement and mounting of these mlccs may cancel their effectiveness due to stray inductance and an increase in trace impedance. () out out in out load,max rms cin v vvv ii ? = , the maximum input voltage ripple and maximum input capacitor rms current occur at the end of the duration of 1 ? d while the upper-side mosfet is in the off state. the input capacitor rms current reaches its maximum at time d. when calculating the maximum input voltage ripple, account for the esr of the input capacitor as follows: v ripple,max = v ripp + ( i load,max esr ) where: v ripp is usually 1% of the minimum voltage input. i load,max is the maximum load current. esr is the equivalent series resistance rating of the input capacitor. inserting v ripple,max into the charge balance equation to calculate the minimum input capacitor requirement gives sw ripple,max load,max in,min f dd v i c )1( ? = or ripple,max sw load,max in,min vf i c 4 = where d = 50%.
adp1870/ADP1871 rev. 0 | page 28 of 44 thermal considerations the adp1870/ADP1871 are used for dc-to-dc, step down, high current applications that have an on-board controller, an on-board ldo, and on-board mosfet drivers. because applications may require up to 20 a of load current delivery and be subjected to high ambient temperature surroundings, the selection of external upper- and lower-side mosfets must be associated with careful thermal consideration to not exceed the maximum allowable junction temperature of 125c. to avoid permanent or irreparable damage if the junction temperature reaches or exceeds 155c, the part enters thermal shutdown, turning off both external mosfets, and does not reenable until the junction temperature cools to 140c (see the on-board low dropout regulator section). in addition, it is important to consider the thermal impedance of the package. because the adp1870/ADP1871 employ an on- board ldo, the ac current (fxcxv) consumed by the internal drivers to drive the external mosfets adds another element of power dissipation across the internal ldo. equation 3 shows the power dissipation calculations for the integrated drivers and for the internal ldo. table 9 lists the thermal impedance for the adp1870/ADP1871, which are available in a 10-lead msop. table 9. thermal impedance for 10-lead msop parameter thermal impedance 10-lead msop ja 2-layer board 213.1c/w 4-layer board 171.7c/w figure 83 specifies the maximum allowable ambient temperature that can surround the adp1870/ADP1871 ic for a specified high input voltage (v in ). figure 83 illustrates the temperature derating conditions for each available switching frequency for low, typical, and high output setpoints for the 10-lead msop package. all temperature derating criteria are based on a maximum ic junction temperature of 125c. 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 5.5 19.017.516.014.513.0 11.5 10.08.5 7.0 maximum allowable ambient temperature (c) v in (v) v out = 0.8v v out = 1.8v v out = high setpoint 600khz 300khz 1mhz 08730-182 figure 83. ambient temperature vs. v in for 10-lead msop (171c/w), 4-layer evb, cin = 4.3 nf (upper-/lower-side mosfet) the maximum junction temperature allowed for the adp1870/ ADP1871 ics is 125c. this means that the sum of the ambient temperature (t a ) and the rise in package temperature (t r ), which is caused by the thermal impedance of the package and the internal power dissipation, should not exceed 125c, as dictated by the following expression: t j = t r t a (1) where: t a is the ambient temperature. t j is the maximum junction temperature. t r is the rise in package temperature due to the power dissipated from within. the rise in package temperature is directly proportional to its thermal impedance characteristics. the following equation represents this proportionality relationship: t r = ja p dr(loss) (2) where: ja is the thermal resistance of the package from the junction to the outside surface of the die, where it meets the surrounding air. p dr(loss) is the overall power dissipated by the ic. the bulk of the power dissipated is due to the gate capacitance of the external mosfets and current running through the on- board ldo. the power loss equations for the mosfet drivers and internal low dropout regulator (see the mosfet driver loss section in the efficiency consideration section) are: p dr(loss) = [ v dr ( f sw c upperfet v dr + i bias )] + [ v reg ( f sw c lowerfet v reg + i bias )] (3) where: c upperfet is the input gate capacitance of the upper-side mosfet. c lowerfet is the input gate capacitance of the lower-side mosfet. i bias is the dc current (2 ma) flowing into the upper- and lower- side drivers. v dr is the driver bias voltage (the low input voltage (v reg ) minus the rectifier drop (see figure 81 )). v reg is the ldo output/bias voltage. ) ()( )()( bias reg total sw reg in lossdr ldodiss ivcfvv p p + ? + = (4) where: p diss(ldo) is the power dissipated through the pass device in the ldo block across vin and vreg. c total is the c gd + c gs of the external mosfet. v reg is the ldo output voltage and bias voltage. v in is the high voltage input. i bias is the dc input bias current. p dr(loss) is the mosfet driver loss.
adp1870/ADP1871 rev. 0 | page 29 of 44 for example, if the external mosfet characteristics are ja (10-lead msop) = 171.2c/w, f sw = 300 khz, i bias = 2 ma, c upperfet = 3.3 nf, c lowerfet = 3.3 nf, v dr = 4.62 v, and v reg = 5.0 v, then the power loss is ( ) [ ] () [] ))002.00.5103.310300(0.5( ))002.062.4103.310300(62.4( 9 3 9 3 )( ++ += + + + = ? ? bias reg lowerfet sw reg bias dr upperfet sw dr lossdr ivcfv ivcfv p = 57.12 mw )002.05103.310300()v5v13( ) () ( 9 3 )( +?= +?= ? bias reg total sw reg in ldodiss ivcfvv p = 55.6 mw mw6.55mw13.77 )()( )( + = + = lossdr ldodiss total diss p p p = 132.73 mw the rise in package temperature (for 10-lead msop) is mw05.132c2.171 )( = = lossdr ja r pt = 22.7c assuming a maximum ambient temperature environment of 85c, c72.107c85c7.22 =+== a rj ttt which is below the maximum junction temperature of 125c. design example the adp1870/ADP1871 are easy to use, requiring only a few design criteria. for example, the example outlined in this section uses only four design criteria: v out = 1.8 v, i load = 15 a (pulsing), v in = 12 v (typical), and f sw = 300 khz. input capacitor the maximum input voltage ripple is usually 1% of the minimum input voltage (11.8 v 0.01 = 120 mv). v ripp = 120 mv v max,ripple = v ripp ? ( i load,max esr ) = 120 mv ? (15 a 0.001) = 45 mv mv105103004 a15 4 3 , , = = ripple max sw max load in,min vf i c = 120 f choose five 22 f ceramic capacitors. the overall esr of five 22 f ceramic capacitors is less than 1 m. i rms = i load /2 = 7.5 a p cin = ( i rms ) 2 esr = (7.5 a) 2 1 m = 56.25 mw inductor determine inductor ripple current amplitude as follows: 3 load l i i ? = 5 a so calculating for the inductor value v2.13 v8.1 10300v5 )v8.1v2.13( ) ( 3 ? = ? = in,max out sw l out in,max v v fi vv l = 1.03 h the inductor peak current is approximately 15 a + (5 a 0.5) = 17.5 a therefore, an appropriate inductor selection is 1.0 h with dcr = 3.3 m (wrth elektronik 7443552100) from table 8 with peak current handling of 20 a. 2 )( l loss dcr idcr p = = 0.003 (15 a) 2 = 675 mw current limit programming the valley current is approximately 15 a ? (5 a 0.5) = 12.5 a assuming a lower-side mosfet r on of 4.5 m and 13 a as the valley current limit from table 7 and figure 71 indicates, a programming resistor (res) of 100 k corresponds to an a cs of 24 v/v. choose a programmable resistor of r res = 100 k for a current- sense gain of 24 v/v. output capacitor assume that a load step of 15 a occurs at the output and no more than 5% is allowed for the output to deviate from the steady state operating point. in this case, the adp1870s advantage is that because the frequency is pseudo-fixed, the converter is able to respond quickly because of the immediate, though temporary, increase in switching frequency. v droop = 0.05 1.8 v = 90 mv assuming that the overall esr of the output capacitor ranges from 5 m to 10 m, )mv90(10300 a15 2 )( 2 3 = ? = droop sw load out vf i c = 1.11 mf therefore, an appropriate inductor selection is five 270 f polymer capacitors with a combined esr of 3.5 m.
adp1870/ADP1871 rev. 0 | page 30 of 44 assuming an overshoot of 45 mv, determine if the output capacitor that was calculated previously is adequate: zero comp comp fr c = 2 1 = 3 3 1025.61010014.32 1 = 250 pf () () 2 2 2 6 2 2 2 )8.1()mv458.1( )a15(101 ) ( )( ?? = ? ? = ? out ovsht out load out v vv il c = 1.4 mf loss calculations duty cycle = 1.8/12 v = 0.15 r on (n2) = 5.4 m choose five 270 f polymer capacitors. t body(loss) = 20 ns (body conduction time) the rms current through the output capacitor is v f = 0.84 v (mosfet forward voltage) a49.1 v2.13 v8.1 10300f1 )v8.1v2.13( 3 1 2 1 ) ( 3 1 2 1 3 , , = ? = ? = maxin out sw out max in rms v v fl vv i c in = 3.3 nf (mosfet gate input capacitance) q n1,n2 = 17 nc (total mosfet gate charge) r gate = 1.5 (mosfet gate input resistance) () [ ] 2 1 load n2(on) n1(on) n1,n2(cl) ird rd p ?+= = (0.15 0.0054 + 0.85 0.0054) (15 a) 2 = 1.215 w the power loss dissipated through the esr of the output capacitor is p cout = ( i rms ) 2 esr = (1.5 a) 2 1.4 m = 3.15 mw 2 )( )( = f load sw loss body loss body vi t t p = 20 ns 300 10 3 15 a 0.84 2 = 151.2 mw feedback resistor network setup it is recommended to use r b = 15 k. calculate r t as follows: k 30 v6.0 v)6.0v8.1( k 15 = ? = t r p sw(loss) = f sw r gate c total i load v in 2 = 300 10 3 1.5 3.3 10 ?9 15 a 12 2 = 534.6 mw compensation network to c a l c u l ate r comp , c comp , and c par , the transconductance parameter and the current-sense gain variable are required. the transconductance parameter (g m ) is 500 a/v, and the current- sense loop gain is ( ) [ ] () [] ))002.00.5103.310300(0.5( ))002.062.4103.310300(62.4( 9 3 9 3 )( ++ += + + + = ? ? bias reg lowerfet sw reg bias dr upperfet sw dr lossdr ivcfv ivcfv p = 57.12 mw a/v33.8 005.024 1 1 = == oncs cs ra g mw6.55 )002.05103.310300()v5v13( ) () ( 9 3 )( = +?= + ? = ? bias reg total sw reg in ldodiss ivcfvv p where a cs and r on are taken from setting up the current limit (see the programming resistor (res) detect circuit and va l le y current-limit setting sections). the crossover frequency is 1/12 th of the switching frequency: p cout = ( i rms ) 2 esr = (1.5 a) 2 1.4 m = 3.15 mw 300 khz/12 = 25 khz 2 )( load loss dcr idcr p = = 0.003 (15 a) 2 = 675 mw the zero frequency is 1/4 th of the crossover frequency: p cin = ( i rms ) 2 esr = (7.5 a) 2 1 m = 56.25 mw 25 khz/4 = 6.25 khz p loss = p n1,n2 + p body(loss) + p sw + p dcr + p dr + p diss(ldo) + p cout + p cin = 1.215 w + 151.2 mw + 534.6 mw + 57.12 mw + 55.6 + 3.15 mw + 675 mw + 56.25 mw = 2.655 w 6.0 8.1 3.810500 1011.11025141.32 1025.61025 1025 2 6 3 3 3 3 3 + = + = ? ? ref out cs m out cross zero cross cross comp v v gg cf ff f r = 100 k
adp1870/ADP1871 rev. 0 | page 31 of 44 external component recommendations the configurations listed in table 10 are with f cross = 1/12 f sw , f zero = ? f cross , r res = 100 k, r bot = 15 k, r on = 5.4 m (bsc042n03ms g), v reg = 5 v (float), and a maximum load current of 14 a. the ADP1871 models listed in table 10 are the psm versions of the device. table 10. external component values marking code sap model adp1870 ADP1871 v out (v) v in (v) c in (f) c out (f) l 1 (h) r c (k) c comp (pf) c par (pf) r top (k) adp1870armz-0.3-r7/ ADP1871armz-0.3-r7 ldw ldg 0.8 13 5 22 2 5 560 3 0.72 47 740 74 5.0 ldw ldg 1.2 13 5 22 2 4 560 3 1.0 47 740 74 15.0 ldw ldg 1.8 13 4 22 2 4 270 4 1.0 47 571 57 30.0 ldw ldg 2.5 13 4 22 2 3 270 4 1.53 47 571 57 47.5 ldw ldg 3.3 13 5 22 2 2 330 5 2.0 47 571 57 67.5 ldw ldg 5 13 4 22 2 330 5 3.27 34 800 80 110.0 ldw ldg 7 13 4 22 2 22 2 + ( 4 47 6 ) 3.44 34 800 80 160.0 ldw ldg 1.2 16.5 4 22 2 4 560 3 1.0 47 740 74 15.0 ldw ldg 1.8 16.5 3 22 2 4 270 4 1.0 47 592 59 30.0 ldw ldg 2.5 16.5 3 22 2 4 270 4 1.67 47 592 59 47.5 ldw ldg 3.3 16.5 3 22 2 2 330 5 2.00 47 592 59 67.5 ldw ldg 5 16.5 3 22 2 2 150 7 3.84 34 829 83 110.0 ldw ldg 7 16.5 3 22 2 22 2 + 4 47 6 4.44 34 829 83 160.0 adp1870armz-0.6-r7/ ADP1871armz-0.6-r7 ldx ldm 0.8 5.5 5 22 2 4 560 3 0.22 47 339 34 5.0 ldx ldm 1.2 5.5 5 22 2 4 270 4 0.47 47 326 33 15.0 ldx ldm 1.8 5.5 5 22 2 3 270 4 0.47 47 271 27 30.0 ldx ldm 2.5 5.5 5 22 2 3 180 8 0.47 47 271 27 47.5 ldx ldm 1.2 13 3 22 2 5 270 4 0.47 47 407 41 15.0 ldx ldm 1.8 13 5 10 9 3 330 5 0.47 47 307 31 30.0 ldx ldm 2.5 13 5 10 9 3 270 4 0.90 47 307 31 47.5 ldx ldm 3.3 13 5 10 9 2 270 4 1.00 47 307 31 67.5 ldx ldm 5 13 5 10 9 150 7 1.76 34 430 43 110.0 ldx ldm 1.2 16.5 3 10 9 4 270 4 0.47 47 362 36 15.0 ldx ldm 1.8 16.5 4 10 9 2 330 5 0.72 47 326 33 30.0 ldx ldm 2.5 16.5 4 10 9 3 270 4 0.90 47 326 33 47.5 ldx ldm 3.3 16.5 4 10 9 330 5 1.0 47 296 30 67.5 ldx ldm 5 16.5 4 10 9 4 47 6 2.0 34 415 41 110.0 ldx ldm 7 16.5 4 10 9 3 47 6 2.0 34 380 38 160.0 adp1870armz-1.0-r7/ ADP1871armz-1.0-r7 ldy ldn 0.8 5.5 5 22 2 4 270 4 0.22 47 223 22 5.0 ldy ldn 1.2 5.5 5 22 2 2 330 5 0.22 47 223 22 15.0 ldy ldn 1.8 5.5 3 22 2 3 180 8 0.22 47 163 16 30.0 ldy ldn 2.5 5.5 3 22 2 270 4 0.22 47 163 16 47.5 ldy ldn 1.2 13 3 10 9 3 330 5 0.22 47 233 23 15.0 ldy ldn 1.8 13 4 10 9 3 270 4 0.47 47 210 21 30.0 ldy ldn 2.5 13 4 10 9 270 4 0.47 47 210 21 47.5 ldy ldn 3.3 13 5 10 9 270 4 0.72 47 210 21 67.5 ldy ldn 5 13 4 10 9 3 47 6 1.0 34 268 27 110.0 ldy ldn 1.2 16.5 3 10 9 4 270 4 0.47 47 326 33 15.0 ldy ldn 1.8 16.5 3 10 9 3 270 4 0.47 47 261 26 30.0 ldy ldn 2.5 16.5 4 10 9 3 180 8 0.72 47 233 23 47.5 ldy ldn 3.3 16.5 4 10 9 270 4 0.72 47 217 22 67.5
adp1870/ADP1871 rev. 0 | page 32 of 44 marking code sap model adp1870 ADP1871 v out (v) v in (v) c in (f) c out (f) l 1 (h) r c (k) c comp (pf) c par (pf) r top (k) ldy ldn 5 16.5 3 10 9 3 47 6 1.0 34 268 27 110.0 ldy ldn 7 16.5 3 10 9 22 2 + 47 6 1.0 34 228 23 160.0 1 see the section and . inductor selection table 11 table 11. recommended inductors 2 22 f murata 25 v, x7r, 1210 grm32er 71e226ke15l (3.2 mm 2.5 mm 2.5 mm). 3 560 f panasonic (sp-series ) 2 v, 7 m, 3.7 a eefue0d561lr (4.3 mm 7.3 mm 4.2 mm). 4 270 f panasonic (sp-series) 4 v, 7 m, 3.7 a eefue0g271lr (4.3 mm 7.3 mm 4.2 mm). 5 330 f panasonic (sp-series) 4 v, 12 m, 3.3 a eefue0g331r (4.3 mm 7.3 mm 4.2 mm). 6 47 f murata 16 v, x5r, 1210 grm32er 61c476ke15l (3.2 mm 2.5 mm 2.5 mm). 7 150 f panasonic (sp-series) 6.3 v, 10 m , 3.5 a eefue0j151xr (4.3 mm 7.3 mm 4.2 mm). 8 180 f panasonic (sp-series) 4 v, 10 m, 3.5 a eefue0g181xr (4.3 mm 7.3 mm 4.2 mm). 9 10 f tdk 25 v, x7r, 1210 c3225x7r1e106m. l (h) dcr (m) i sat (a) dimension (mm) manufacturer model number 0.12 0.33 55 10.2 7 wrth elektronik 744303012 0.22 0.33 30 10.2 7 wrth elektronik 744303022 0.47 0.67 50 13.2 12.8 wrth elektronik 744355147 0.72 1.3 35 10.5 10.2 wrth elektronik 744325072 0.9 1.6 28 13 12.8 wrth elektronik 744355090 1.2 1.8 25 10.5 10.2 wrth elektronik 744325120 1.0 3.3 20 10.5 10.2 wrth elektronik 7443552100 1.4 3.2 24 14 12.8 wrth elektronik 744318180 2.0 2.6 22 13.2 10.8 wrth elektronik 7443551200 0.8 2.5 16.5 12.5 12.5 aic technology cep125u-r80 table 12. recommended mosfets v gs = 4.5 v r on (m) i d (a) v ds (v) c in (nf) q total (nc) package manufacturer model number upper-side mosfet (q1/q2) 5.4 47 30 3.2 20 pg-tdson8 infineon bsc042n03ms g 10.2 53 30 1.6 10 pg-tdson8 infineon bsc080n03ms g 6.0 19 30 35 so-8 vishay si4842dy 9 14 30 2.4 25 so-8 international rectifier irf7811 lower-side mosfet (q3/q4) 5.4 47 30 3.2 20 pg-tdson8 infineon bsc042n03ms g 10.2 82 30 1.6 10 pg-tdson8 infineon bsc080n03ms g 6.0 19 30 35 so-8 vishay si4842dy
adp1870/ADP1871 rev. 0 | page 33 of 44 layout considerations the performance of a dc-to-dc converter depends highly on how the voltage and current paths are configured on the printed circuit board (pcb). optimizing the placement of sensitive analog and power components is essential to minimize output ripple, maintain tight regulation specifications, and reduce pwm jitter and electromagnetic interference. figure 84 shows the schematic of a typical adp1870/ADP1871 used for a high current application. blue traces denote high current pathways. vin, pgnd, and v out traces should be wide and possibly replicated, descending down into the multiple layers. vias should populate, mainly around the positive and negative terminals of the input and output capacitors, alongside the source of q1/q2, the drain of q3/q4, and the inductor. murata: (high voltage input capacitors) 22f, 25v, x7r, 1210 grm32er71e226ke15l panasonic: (output capacitors) 270f, sp-series, 4v, 7m ? eefue0g271lr infineon mosfets: bsc042n03ms g (lower side) bsc080n03ms g (upper side) wrth inductors: 1h, 3.3m ? , 20a 7443552100 r5 100k? q3 q4 q1 q2 high voltage input v in = 12v c12 100nf v out = 1.8v, 15a c3 22f c4 22f c5 22f c6 22f c7 22f c8 n/a c9 n/a c23 270f + c22 270f + c21 270f + c20 270f + c27 n/a c14 to c19 n/a + c26 n/a + c25 n/a + c24 n/a + 1.0h r6 2 ? c13 1.5nf r1 30k ? r2 15k? r4 0 ? v out 1 vin 10 bst 2 comp/en 9 sw 3 fb 8 drvh 4 gnd 7 pgnd 5 vreg 6 drvl adp1870/ ADP1871 c c 571pf c f 57pf r c 47k? c1 1f c28 10f c2 0.1f jp3 08730-081 figure 84. adp1870 high current evaluation board sc hematic (blue traces indicate high current paths)
adp1870/ADP1871 rev. 0 | page 34 of 44 08730-082 output capacitors are mounted on the rightmost area of the evb, wrapping back around to the main power ground plane, where it meets with the negative terminals of the input capacitors input capacitors are mounted close to drain of q1/q2 and source of q3/q4. bypass power capacitor (c1) for vreg bias decoupling and high frequency capacitor (c2) as close as possible to the ic. sensitive analog components located far from the noisy power section. separate analog ground plane for the analog components (that is, compensation and feedback resistors). figure 85. overall layout of the adp1870 high current evaluation board
adp1870/ADP1871 rev. 0 | page 35 of 44 08730-084 figure 86. layer 2 of evaluation board
adp1870/ADP1871 rev. 0 | page 36 of 44 top resistor feedback tap 08730-083 v out sense tap line extending back to the top resistor in the feedback divider network (see figure 86 to figure 88). this overlaps with pgnd sense tap line extending back to the analog plane (see figure 88, layer 4 for pgnd tap). figure 87. layer 3 of evaluation board
adp1870/ADP1871 rev. 0 | page 37 of 44 08730-085 bottom resistor tap to the analog ground plane pgnd sense tap from negative terminals of output bulk capacitors. this track placement should be directly below the v out sense line from figure 84. figure 88. layer 4 (bottom layer) of evaluation board ic section (left side of evaluation board) a dedicated plane for the analog ground plane (gnd) should be separate from the main power ground plane (pgnd). with the shortest path possible, connect the analog ground plane to the gnd pin (pin 4). this plane should be on only the top layer of the evaluation board. to avoid crosstalk interference, there should not be any other voltage or current pathway directly below this plane on layer 2, layer 3, or layer 4. connect the negative terminals of all sensitive analog components to the analog ground plane. examples of such sensitive analog com- ponents include the resistor dividers bottom resistor, the high frequency bypass capacitor for biasing (0.1 f), and the compensation network. mount a 1 f bypass capacitor directly across the vreg pin (pin 5) and the pgnd pin (pin 7). in addition, a 0.1 f should be tied across the vreg pin (pin 5) and the gnd pin (pin 4). power section as shown in figure 85 , an appropriate configuration to localize large current transfer from the high voltage input (v in ) to the output (v out ) and then back to the power ground is to put the v in plane on the left, the output plane on the right, and the main power ground plane in between the two. current transfers from the input capacitors to the output capacitors, through q1/q2, during the on state (see figure 89 ). the direction of this current (yellow arrow) is maintained as q1/q2 turns off and q3/q4 turns on. when q3/q4 turns on, the current direction continues to be maintained (red arrow) as it circles from the bulk capacitors power ground terminal to the output capacitors, through the q3/q4. arranging the power planes in this manner minimizes the area in which changes in flux occur if the current through q1/q2 stops abruptly. sudden changes in flux, usually at source terminals of q1/q2 and drain terminal of q3/q4, cause large dv/dts at the sw node. the sw node is near the top of the evaluation board. the sw node should use the least amount of area possible and be away from any sensitive analog circuitry and components because this is where most sudden changes in flux density occur. when possible, replicate this pad onto layer 2 and layer 3 for thermal relief and eliminate any other voltage and current pathways directly beneath the sw node plane. populate the sw node plane with vias, mainly around the exposed pad of the inductor terminal and around the perimeter of the source of q1/q2 and the drain of q3/q4. the output voltage power plane (v out ) is at the right- most end of the evaluation board. this plane should be replicated, descending down to multiple layers with vias surrounding the inductor terminal and the positive terminals of the output bulk capacitors. ensure that the negative terminals of the output capacitors are placed close to the main power ground (pgnd), as previously mentioned. all of these points form a tight circle
adp1870/ADP1871 rev. 0 | page 38 of 44 (component geometry permitting) that minimizes the area of flux change as the event switches between d and 1 ? d. vout sw vin pgnd 08730-086 figure 89. primary current pathways during the on state of the upper-side mosfet (left arrow) and the on state of the lower-side mosf et (right arrow) differential sensing because the adp1870/ADP1871 operate in valley current- mode control, a differential voltage reading is taken across the drain and source of the lower-side mosfet. the drain of the lower-side mosfet should be connected as close as possible to the sw pin (pin 9) of the ic. likewise, the source should be connected as close as possible to the pgnd pin (pin 7) of the ic. when possible, both of these track lines should be narrow and away from any other active device or voltage/current path. 08730-087 layer 1: sense line for sw (drain of lower mosfet) layer 1: sense line for pgnd (source of lower mosfet) figure 90. drain/source tracking tapp ing of the lower-side mosfet for cs amp differential sensing (yellow sense line on layer 2) differential sensing should also be applied between the outermost output capacitor to the feedback resistor divider (see figure 87 and figure 88 ). connect the positive terminal of the output capacitor to the top resistor (r t ). connect the negative terminal of the output capacitor to the negative terminal of the bottom resistor, which connects to the analog ground plane as well. both of these track lines, as previously mentioned, should be narrow and away from any other active device or voltage/ current path.
adp1870/ADP1871 rev. 0 | page 39 of 44 typical applications circuits 15 a, 300 khz high current application circuit murata: (high voltage input capacitors) 22f, 25v, x7r, 1210 grm32er71e226ke15l panasonic: (output capacitors) 270f, sp-series, 4v, 7m ? eefue0g271lr infineon mosfets: bsc042n03ms g (lower side) bsc080n03ms g (upper side) wrth inductors: 1h, 3.3m ? , 20a 7443552100 r5 100k ? q3 q4 q1 q2 high voltage input v in = 12v c12 100nf v out = 1.8v, 15a c3 22f c4 22f c5 22f c6 22f c7 22f c8 n/a c9 n/a c23 270f + c22 270f + c21 270f + c20 270f + c27 n/a c14 to c19 n/a + c26 n/a + c25 n/a + c24 n/a + 1.0h r6 2 ? c13 1.5nf r1 30k ? r2 15k ? r4 0 ? v out 1 vin 10 bst 2 comp/en 9 sw 3 fb 8 drvh 4 gnd 7 pgnd 5 vreg 6 drvl adp1870/ ADP1871 c c 571pf c f 57pf r c 47k ? c1 1f c28 10f c2 0.1f jp3 08730-088 figure 91. application circuit for 12 v input, 1.8 v output, 15 a, 300 khz (q2/q4 no connect) 5.5 v input, 600 khz application circuit murata: (high voltage input capacitors) 22f, 25v, x7r, 1210 grm32er71e226ke15l panasonic: (output capacitors) 180f, sp-series, 4v, 10m ? eefue0g181xr infineon mosfets: bsc042n03ms g (lower side) bsc080n03ms g (upper side) wrth inductors: 0.47h, 0.8m ? , 50a 744355147 r5 100k ? q3 q4 q1 q2 high voltage input v in = 5.5v c12 100nf v out = 2.5v, 15a c3 22f c4 22f c5 22f c6 22f c7 22f c8 n/a c9 n/a c23 n/a + c22 180f + c21 180f + c20 180f + c27 n/a c14 to c19 n/a + c26 n/a + c25 n/a + c24 n/a + 0.47h r6 2 ? c13 1.5nf r1 30k ? r2 15k ? r4 0 ? v out 1 vin 10 bst 2 comp/en 9 sw 3 fb 8 drvh 4 gnd 7 pgnd 5 vreg 6 drvl adp1870/ ADP1871 c c 571pf c f 57pf r c 47k ? c1 1f c28 10f c2 0.1f jp3 08730-089 figure 92. application circuit for 5.5 v input, 2.5 v output, 15 a, 600 khz (q2/q4 no connect)
adp1870/ADP1871 rev. 0 | page 40 of 44 300 khz high current application circuit murata: (high voltage input capacitors) 22f, 25v, x7r, 1210 grm32er71e226ke15l sanyo oscon: 270f, 16svpc270m, 14m ? panasonic: (output capacitors) 270f, sp-series, 4v, 7m ? eefue0g271lr infineon mosfets: bsc042n03ms g (lower side) bsc080n03ms g (upper side) wrth inductors: 0.72h, 1.65m ? , 35a 744325072 r5 100k? q3 q4 q1 q2 high voltage input v in = 13v c12 100nf v out = 1.8v, 12a c3 22f c4 22f c5 22f c6 n/a c7 n/a c8 n/a c9 270f c23 270f + c22 270f + c21 270f + c20 270f + c27 n/a c14 to c19 n/a + c26 n/a + c25 n/a + c24 n/a + 1.4h r6 2 ? c13 1.5nf r1 30k ? r2 15k ? r4 0 ? v out 1 vin 10 bst 2 comp/en 9 sw 3 fb 8 drvh 4 gnd 7 pgnd 5 vreg 6 drvl adp1870/ ADP1871 c c 528pf c f 53pf r c 43k? c1 1f c28 10f c2 0.1f jp3 08730-090 figure 93. application circuit for 13 v input, 1.8 v output, 12 a, 300 khz (q2/q4 no connect)
adp1870/ADP1871 rev. 0 | page 41 of 44 outline dimensions compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 94. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding adp1870armz-0.3-r7 ?40c to +125c 10-lead mini small outline package [msop] rm-10 ldw adp1870armz-0.6-r7 ?40c to +125c 10-lead mini small outline package [msop] rm-10 ldx adp1870armz-1.0-r7 ?40c to +125c 10-lead mini small outline package [msop] rm-10 ldy ADP1871armz-0.3-r7 ?40c to +125c 10-lead mini small outline package [msop] rm-10 ldg ADP1871armz-0.6-r7 ?40c to +125c 10-lead mini small outline package [msop] rm-10 ldm ADP1871armz-1.0-r7 ?40c to +125c 10-lead mini small outline package [msop] rm-10 ldn adp1870-0.3-evalz evaluation board adp1870-0.6-evalz evaluation board adp1870-1.0-evalz evaluation board ADP1871-0.3-evalz evaluation board ADP1871-0.6-evalz evaluation board ADP1871-1.0-evalz evaluation board 1 z = rohs compliant part.
adp1870/ADP1871 rev. 0 | page 42 of 44 notes
adp1870/ADP1871 rev. 0 | page 43 of 44 notes
adp1870/ADP1871 rev. 0 | page 44 of 44 notes ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08730-0-3/10(0)

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